11-Bit 200MSps Pipeline Analog-to-Digital Converter

This ECEN 607 final project implements an 11-bit pipeline ADC targeting 200 MSps with an aggressive power budget (under 10 mW). The design uses a 2.5-bit per stage pipeline with a front-end sample-and-hold amplifier (SHA), redundant digital recombination, and per-stage residue amplification. The implementation focuses on amplifier and switch linearity, low-noise sampling, and efficient comparator design.

Full Project Report

project_report

Theoretical Background

Pipeline ADCs combine moderate per-stage resolution with high throughput by distributing bit conversion across sequential stages. Each stage resolves a small number of bits, subtracts an analog contribution (via a sub-DAC), amplifies the residue, and passes it to the next stage. Redundancy (e.g., 2.5-bit stages) relaxes comparator offset and amplifier settling requirements, trading a small area/power overhead for improved yield and reduced analog precision requirements.

Key analog building blocks include low-distortion bootstrapped switches for linear sampling, high-gain SHA amplifiers to buffer the input, fast and low-power residue amplifiers for MDAC settling, and strong-ARM style dynamic comparators with preamplification for stage decisions. Effective common-mode feedback (CMFB) and capacitor sizing based on thermal noise are crucial to achieve robust performance at high sample rates.

Architecture and Design Highlights

The ADC uses a 2.5-bit/stage topology with a front-end flip-over SHA implemented using a recycling folded-cascode (RFC) amplifier with gain-boosting. Five pipeline stages produce the 11-bit word after digital alignment and recombination logic. Non-overlapping clocks minimize charge injection and switching errors.

Design choices and highlights:

  • Per-stage resolution: 2.5-bit/stage with digital redundancy and recombination.
  • SHA amplifier: Recycling folded-cascode with gain-boost for high DC gain and required GBW.
  • Residue amplifier: RFC core used for power-efficient residue amplification; feedforward amplifier evaluated but not used due to power cost.
  • Switching: Bootstrapped switches at the input to improve linearity across a wide voltage range.
  • Comparators: Strong-ARM latch preceded by a preamplifier and followed by an RS latch to hold decisions.
  • Digital: Verilog-A models for thermometer-to-binary and sub-DAC logic; ideal 11-bit DAC used for testing SNDR/ENOB.
  • Unit capacitor: 200 fF chosen based on thermal noise analysis.

Simulation & Measured Results

System modeling in Simulink guided amplifier GBW and noise requirements. Cadence-level simulations validated the analog blocks and full-pipeline testbenches. Key measured/simulated metrics are summarized below.

  • Sample rate: 200 MSps
  • SNDR: 45.4 dB
  • ENOB: 7.24 bits
  • SFDR: 53.4 dB
  • Total power: 9.78 mW (SHA 2 mW, residue amps 5.32 mW, switches/comparators 3.46 mW)
  • Figure-of-Merit (FoM): 145.5 dB
  • Unit cap: 200 fF

Conclusion

The implemented pipeline ADC demonstrates a power-efficient architecture for medium-speed, moderate-resolution conversion. Although the ENOB falls short of the 11-bit goal (7.24 bits measured), the overall power consumption is near target and the FoM is competitive for an uncalibrated design. The report recommends the addition of post-calibration (e.g., adaptive LMS-based schemes) to recover multiple bits of resolution and further algorithmic compensation to correct amplifier nonidealities.

Future work includes implementing digital calibration, optimizing amplifier topologies for lower distortion at the same power, and transitioning from Verilog-A models to synthesized digital back-end logic at minimum sizing to validate overall power and timing.